Table of Contents

Abstract

Declaration

Copyright and Intellectual Property Rights

Acknowledgements

The Author

Chapter 1: SCALP: A Superscalar Asynchronous Low-Power Processor

• 1.1: The Importance of Power Efficiency

• 1.2: Low Power Design Techniques

  • 1.2.1: Low-Level Power Efficiency

    • Process Technology

    • Transistor Level Design

    • Charge Recovery and Adiabatic Systems

    • Logic Optimisation

    • Supply Voltage Adjustment

    • Parallelism

    • Precomputation

    • Clocking Schemes and Asynchronous Logic

  • 1.2.2: Higher-Level Power Efficiency: Microprocessors

    • External Memory Bandwidth

    • Cache Characteristics

    • Datapath Arrangement

• 1.3: Previous Low Power Processors

• 1.4: Overview of the Thesis

Chapter 2: Reducing Transitions

• 2.1: Code Density

  • 2.1.1: Variable Length Instructions

  • 2.1.2: Register Specifiers

  • 2.1.3: Previous High Code Density Processors

    • D16

    • Thumb

    • Transputer

• 2.2: Datapath Activity

Chapter 3: Parallelism

• 3.1: Parallelism and Power

• 3.2: Power, Parallelism and Cost

• 3.3: Parallelism in Special Purpose Processors

• 3.4: Parallelism in General Purpose Processors

• 3.5: Pipelining

  • 3.5.1: Branch Instructions

  • 3.5.2: Dependencies

  • 3.5.3: Different Pipeline Arrangements

    • Shorter Pipelines

    • Longer Pipelines

• 3.6: Superscalar Parallelism

  • 3.6.1: Dependencies

  • 3.6.2: Branch Instructions

  • 3.6.3: Observations

  • 3.6.4: Simpler forms of Multiple Functional Unit Parallelism

• 3.7: Speculative Execution

Chapter 4: Asynchronous Logic

• 4.1: Asynchronous Logic and Power Efficiency

  • 4.1.1: Asynchronous Circuits can be Faster

  • 4.1.2: Asynchronous Circuits can be Smaller

  • 4.1.3: Asynchronous Logic in Variable Demand Systems

  • 4.1.4: Asynchronous Logic and Dynamic Supply Voltage Adjustment

  • 4.1.5: Asynchronous Logic Doesn't Waste Transitions

  • 4.1.6: Other benefits of Asynchronous Logic

  • 4.1.7: Tangram and the Philips DCC Error Corrector

  • 4.1.8: Conclusion

• 4.2: Asynchronous Pipelines

  • 4.2.1: Forwarding in Asynchronous Pipelines

  • 4.2.2: Conditional Forwarding

  • 4.2.3: Explicit Forwarding

• 4.3: Asynchronous Superscalar Parallelism

  • 4.3.1: Simple Superscalar Structures

  • 4.3.2: Superscalar Forwarding

• 4.4: Previous Asynchronous Processors

  • The Caltech Asynchronous Processor

  • AMULET1 and AMULET2

  • NSR

  • Fred

  • Counterflow Pipeline Processor

  • Hades

  • ECSTAC

  • TITAC

  • ST_RISC

  • FAM

  • STRiP

  • 4.4.1: Observations

Chapter 5: The SCALP Architecture

• 5.1: Explicit Forwarding and Non-Global Registers

• 5.2: Deadlocks and Determinism

• 5.3: Other SCALP Features

• 5.4: A SCALP Instruction Set

• 5.5: The SCALP Programming Model

• 5.6: Interrupts and Exceptions

• 5.7: Related Work

  • 5.7.1: Stack Processors

  • 5.7.2: Architectural Queues

  • 5.7.3: Explicit Forwarding

Chapter 6: Implementation

• 6.1: Asynchronous Design Styles

  • 6.1.1: Timing Models for Control Circuits

  • 6.1.2: Timing Models for Datapaths

  • 6.1.3: Asynchronous Signalling Protocols

• 6.2: Implementation Methodology

• 6.3: Overview of the Design

  • Memory Interface

  • Fetcher

  • FIG Fifo

  • Issuer

  • Instruction Queues

  • Operand Queues

  • Branch Unit

  • ALU

  • Load/Store Unit

  • Move Unit

  • Register Bank

  • Result Queues

  • Result Routing Network

• 6.4: Implementation of the Instruction Issuer

  • 6.4.1: The Need for Parallelism

  • 6.4.2: The Proposed Solution

  • 6.4.3: The Implementation

    • Token Block

    • Decode Block

    • Sequence Block

  • 6.4.4: Adding Branch Instructions

  • 6.4.5: Adding Variable Length Instructions

  • 6.4.6: Performance of the Instruction Issuer

    • Architectural Performance

    • Implementation Performance

• 6.5: Implementation of the Result Routing Network

  • Arbitration

  • Other Organisations

• 6.6: Functional Units

• 6.7: Size of the Implementation

Chapter 7: Evaluation

• 7.1: Evaluation Procedure

  • 7.1.1: Test Stimuli

    • Instruction Sequences

    • Example Programs

  • 7.1.2: Evaluation Programs

    • Pipeline Visualisation

    • Resource Utilisation

    • Instruction Rate

  • 7.1.3: Use of the Geometric Mean

• 7.2: Code Density

• 7.3: Pipeline Performance

  • 7.3.1: Performance of Isolated Stages

    • FIG Fetch

    • Instruction Issue

    • Functional Units

    • Result Network

  • 7.3.2: Overall Performance

    • Starvation and Blocking

    • Pipeline Performance with Branches

  • 7.3.3: Measured Performance

    • Instruction Sequences

    • Example Programs

  • 7.3.4: Conclusion

• 7.4: Functional Unit Parallelism

• 7.5: Comparative Performance

• 7.6: Evaluating the performance of Asynchronous Logic

• 7.7: Power

  • 7.7.1: High code density

  • 7.7.2: Parallelism

  • 7.7.3: Asynchronous Implementation

  • 7.7.4: Variable width datapath operations

  • 7.7.5: Summary

• 7.8: Evaluating the SCALP Programming Model

Chapter 8: Conclusions

• 8.1: Summary

  • Motivation

  • Architecture

  • Implementation

• 8.2: Improving the SCALP Architecture

• 8.3: Improving the SCALP Implementation

  • 8.3.1: Branch Prediction

  • 8.3.2: Faster Asynchronous Logic

  • 8.3.3: Variable Length Instructions

  • 8.3.4: Functional Unit Pipelining

• 8.4: The Future of SCALP

• 8.5: SCALP and Conventional Architectures

• 8.6: Conclusions

Appendix A: Benchmarks

References