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APT Advanced Processor Technologies Research Group

Scalable Object-Aware Hardware Transactional Memor

Behram Khan, Matthew Horsnell, Mikel Lujan and Ian Watson


A Hardware Transactional Memory (HTM) aids the construction of lock-free regions within applications with fewer concerns about correctness and potentially greater performance through optimistic concurrency. Object-aware hardware adds a level of indirection to memory accesses, memory addresses become a combination of the object being accessed and the offset within it. The hardware maintains a mapping from objects to memory locations just as a mapping from virtual to real memory is handled through page tables. In a scalable object-aware system the directories are addressed by objects identifiers. In this paper we extend a scalable object-aware memory system to implement a HTM. Our object-aware protocol permits locks on directories to be avoided for objects only read during a transaction. Working at the granularity of an object allows entries within the directories to be associated with multiple cache lines, as opposed to one, and reduce the amount of network traffic. Finally, our commit protocol dispenses with the need for a centrally controlled transaction ID order.