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Critical path analysis in data-driven asynchronous pipelines

Hong-Guang Ren, Zhi-Ying Wang, Wei Shi, Doug Edwards


A direct way to improve the performance of a pipelined system is to optimize the critical paths. In this paper we firstly define the critical path analysis problem in data-driven asynchronous pipelines and propose an efficient method to solve it. The defined critical path analysis problem is solved by leveraging the modularity of asynchronous circuits at two levels: the block level and the gate level. An automatic algorithm is proposed both to calculate the delay distributions and to detect the critical paths in asynchronous pipelines. A critical-path-aware latch insertion strategy is implemented in a syntax-directed data-driven asynchronous circuits design tool - Teak. The efficiency of the method is demonstrated on two complex asynchronous designs - a 32×32-bit radix-8 Booth multiply-accumulate(MAC) unit and a 32-bit microprocessor named Sparkler. Simulation results show that the critical path analysis offers an insight to the delay distributions in data-driven asynchronous pipelines and a valuable guidance for performance improvement. The throughput improvement via the critical-path-aware latch insertion can achieve as high as 30.0% and 43.5% compared to the base designs of the MAC unit and the Sparkler respectively.

DOI-Link IEEE Copyright