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A Programmable Adaptive Router for a GALS Parallel System

J. Wu, S.B. Furber and J.D. Garside


This paper describes a router which is the key component of a scalable asynchronous on-chip and inter-chip communication infrastructure for an application-specific parallel computing system. We use this system as a universal platform for real time simulations of large-scale neural networks. The communications router supports multiple routing algorithms, and is pipelined to boost its throughput. The design considerations emphasize programmability and adaptive routing. Programmability offers a highly configurable architecture suited to a range of different applications. Adaptive routing offers a fault-tolerance capability that is highly desirable for large-scale digital computational systems. In addition, many neural applications are inherently fault-tolerant. Therefore, the router may selectively drop some packets in order to maintain a reasonable Quality of Service (QoS). The design objectives are achieved through the use of a synchronous elastic pipeline controlled by a handshake protocol which gives the flexibility to stall the traffic flow during run-time for configuration and other purposes, or to redirect the traffic flow to an alternative link to reroute around a failed or congested link.

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