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SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip

L. A. Plana, D. Clark, S. Davidson, S. Furber, J. Garside, E. Painkras, J. Pepper, S. Temple and J. Bainbridge


The design and implementation of Globally Asynchronous Locally Synchronous Systems-on-Chip is a challenging activity. The large size and complexity of the systems require the use of Computer-Aided Design (CAD) tools but, unfortunately, most tools do not work adequately with asynchronous circuits. This paper describes the successful design and implementation of SpiNNaker, a GALS multi-core system-on-chip. The processes was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way which allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met.