An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Sim ulator

Plana, Luis A.; Bainbridge, John; Furber, Steve; Salisbury, Sean; Shi, Yebin; Wu, Jian

Abstract

The real-time modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication throughput. SpiNNaker is a scalable, multi-chip system designed for this purpose with an efficient multicast communications infrastructure inspired by neurobiology. SpiNNaker uses a self-timed, packet-switched Network-on-Chip to emulate the very high connectivity of biological systems. The packets represent neural spikes and are source-routed, i.e., they only carry information about the issuing neuron and the network infrastructure is responsible for delivering them to their destinations. The heart of the communications NoC is a multicast router based on a masked associative route look-up table. A novel bandwidth aggregation scheme is used to optimize the utilization of the available NoC bandwidth to deliver an incoming packet to router on every clock cycle. The self-timed implementation of the fabric allows the seamless extension of the on-chip communications system to include the inter-chip links.

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