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System Level Modelling for SpiNNaker CMP System

M.M. Khan, E. Painkras, X. Jin, L.A. Plana, J.V. Woods and S.B. Furber


The SpiNNaker massively parallel Chip-multiprocessor (CMP) system is a novel SoC architecture, being designed specifically for large-scale neural simulations in real-time. We have developed a multi-CMP complete system's simulation for the SpiNNaker computing system using SystemC Transaction Level Modelling (TLM) to analyze architectural tradeoffs, verify the design, and develop/test intended applications. The model has been very helpful in understanding system-level behaviour in the early stages of the design which was not possible with a Hardware Description Language (HDL) simulation for the development time, performance and scale of simulation. We could simulate a system with up to 200 SpiNNaker CMPs to test a parallel distributed application developed for the actual hardware. The model helped in refining SpiNNaker's design while providing a platform for developing its applications in parallel with the hardware design.

IEEE Copyright