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TERAFLUX: Harnessing dataflow in next generation teradevices

Roberto Giorgi and Rosa M. Badia and Francois Bodin and Albert Cohen and Paraskevas Evripidou and Paolo Faraboschi and Bernhard Fechner and Guang R. Gao and Arne Garbade and Rahul Gayatri and Sylvain Girbal and Daniel Goodman and Behran Khan and Souad Koliai and Joshua Landwehr and Nhat Minh Le and Feng Li and Mikel Lujan and Avi Mendelson and Laurent Morin and Nacho Navarro and Tomasz Patejko and Antoniu Pop and Pedro Trancoso and Theo Ungerer and Ian Watson and Sebastian Weis and Stephane Zuckerman and Mateo


The improvements in semiconductor technologies are gradually enabling extreme-scale systems such as teradevices (i.e., chips composed by 1000 billion of transistors), most likely by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper presents an overview of the research carried out by the TERAFLUX partners and some preliminary results. Our platform comprises 1000+ general purpose cores per chip in order to properly explore the above challenges. An architectural template has been proposed and applications have been ported to the platform. Programming models, compilation tools, and reliability techniques have been developed. The evaluation is carried out by leveraging on modifications of the HP-Labs COTSon simulator.