Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits
Zheng Xie, D.A.Edwards
Abstract
The intrinsic variability of nano-scale integrated circuit (IC) technology must be taken into account when analyzing circuit designs to predict likely yield. Monte Carlo (MC) and quasi-MC (QMC) based statistical techniques aim to do this by analysing many randomized copies of the circuit. The randomization must model many forms of variability that are to be expected in nano-CMOS technology which include âatomisticâ effects without intra-die correlation and also effects with intra-die correlation due to the proximity of neighbouring devices. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. Principal components analysis (PCA) and âStatistical Behavioural Circuit Blocks (SBCB)â are means of reducing the dimensionality of the analysis, and these may be combined with an implementation of âStatistical Blockade (SB)â to achieve significant reduction in the computational costs. A computation time reduction of 98.7% has thus been achieved for a commonly used asynchronous circuit element and QMC analysis with âlow discrepancy sequences (LDS)â have been introduced for further computation reduction. QMC analysis using SBCB behavioural models with SB has been evaluated by applying it to more complex examples and comparing the results with those of transistor level simulations. The analysis of SRAM arrays is taken as a case study for VLSI circuits containing up to 1536 transistors, modeled with parameters appropriate to 35nm technology. A saving of 99.85% in computation time was obtained with larger circuits.!