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APT Advanced Processor Technologies Research Group

Early Output Logic and Anti-Tokens

Charles Brej


Asynchronous logic has for some time been promoted as being able to take advantage of average case performance. Unfortunately the overheads of using asynchronous techniques, such as the return to zero phase and unnecessary synchronisations, have often outweighed the benefits. The aim of the research described is to take full advantage of the performance benefits attainable through the use of asynchronous methodologies, then to overcome the overheads introduced. The thesis introduces the Early Output design methodology which allows the generation of circuits which synchronise the production of outputs with the minimal set of inputs, thus generating the result as soon as possible. The throughput problem is tackled through a series of optimisations. The optimisations allow the removal of unnecessary synchronisation points which degrade performance. One novel optimisation is the anti-token latch which allows further improvements in performance by inhibiting operations once their results are found to be unnecessary. To determine where the optimisations should be applied, a novel dynamic analysis technique was developed. This targets improving average case performance through simulating the design running a benchmark and attaining the Slowest Path (a sequence of elements which contributed to the delay of the simulation run). The effect of the optimisation is demonstrated on a range of circuits presenting each optimisation's applicability to various commonly used structures. The result of these techniques is a system capable of generating circuits which generally perform faster than their synchronous equivalents.

The thesis is available as PDF (935KB).