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APT Advanced Processor Technologies Research Group

Implementing Balsa Handshake Circuits

Andrew Bardsley


Two major additions to the Balsa asynchronous circuit synthesis system are presented.

Firstly, a new back-end for generating VLSI and FPGA implementations of Balsa descriptions is described. This back-end allows parameterised generation of handshake components from template descriptions.

Secondly, a new method for producing handshake circuits which are better optimised during construction is described. A number of new handshake components are introduced. Each of these components, by virtue of their greater degree of parameterisation, can replace clusters of existing handshake components. These parameterised components are used to implement bespoke synchronisation, encoding/decoding and bitwise word division/construction operations using component specific optimisations which replace the, potentially dangerous, gate level optimisations previously used.

The design and VLSI implementation of a substantial test design using Balsa, a 32 channel DMA controller, is also presented. This DMA controller was constructed as part of the AMULET3i asynchronous processor macrocell. It is a hybrid synchronous/asynchronous design using a combination of full custom, hand designed standard cell and Balsa synthesis. The AMULET3i macrocell has been fabricated as part of the DRACO communications controller IC.

A simplified, fully asynchronous, version of this DMA controller is also presented in order to illustrate the use of the optimisations presented in the thesis.

The thesis is available in PDF by ftp (1099KB).