Advanced Processor Technologies Home
APT Advanced Processor Technologies Research Group

Low Overhead Dynamic Binary Translation for ARM

Bernard Amanieu d'Antras


Driven by Moore's Law, many computer architectures -- ARM, x86, MIPS, PowerPC, SPARC -- have evolved from 32-bit to 64-bit. To support existing applications, these have all kept support for a 32-bit compatibility mode. However, this comes at a cost in hardware complexity, power consumption and development time.

Dynamic binary translation -- recompiling binaries into the new instruction set at runtime -- can be used instead of specific hardware for this purpose. While this approach has previously been used to assist architecture transition, these translators have all traded-off performance and transparency, a measure of how accurately they emulate the 32-bit environment.

This thesis addresses ARM's transition from AArch32 to AArch64 through MAMBO-X64, a dynamic binary translator developed to support this transition. A range of novel optimizations were devised to improve translation performance while maintaining strict transparency. This follows a common theme of exploiting existing hardware features such as hardware return prediction, virtual memory and virtualization extensions to offset translation overheads. HyperMAMBO-X64 -- a variant of MAMBO-X64 integrated in a hypervisor -- was also developed to support system-level translation while remaining transparent to guest operating systems.

Results demonstrate that the cost of binary translation is reduced, delivering performance competitive with the manufacturer's hardware. Performance in several benchmarks even exceeds that from the integrated compatibility mode. Thus MAMBO-X64 not only provides a means for architectural upgrade, but also an alternative to the expense of the legacy support currently employed.

The thesis is available as PDF (2.2 MB) from July 2017.