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APT Advanced Processor Technologies Research Group

Asynchronous Techniques for Power-Adaptive Processing

Aris Efthymiou


Power consumption has become a significant concern in the design of digital integrated circuits. A solution to the need for both low-power and high-performance systems is power-adaptivity, the capability of a system to dynamically scale its power consumption according to the demand for processing.

This thesis examines micro-architectural techniques that can be used to build an asynchronous, power-adaptive microprocessor. Two main techniques are presented using AMULET3, an asynchronous processor designed at the University of Manchester, as a basis for development and evaluation. The first controls the pipeline occupancy using a token mechanism, while the second enables adjacent pipeline stages to be merged, thus altering the processor's micro-architecture. These techniques manage the processor's power consumption by controlling its speculation depth. The execution time may be increased but, if the method is applied to programs with slack time, the user-perceived performance will not be degraded. Hardware-based methods for controlling the speculation depth dynamically are also investigated.

A large proportion of a system's power budget is also attributable to its memory. As a step towards the design of a power-efficient memory system, a self-timed, adaptive, Content-Addressable Memory (CAM), for use in associative caches, is developed that consumes almost a quarter of the power of a standard CAM.

Together these techniques exploit asynchronous design in a way which would be difficult in a clocked system. Results are presented which show that such techniques are of significant benefit, but only in certain classes of programs; thus for a general-purpose processor the ability to control the micro-architecture dynamically adds more operating flexibility and potentially greater energy and power savings.

The thesis is available by ftp in pdf (1.2MB) form.