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Computation Reduction for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

Zheng Xie


The intrinsic atomistic variability of nano-scale integrated circuit (IC) technology must be taken into account when analysing circuit designs to predict likely yield. These ‘atomistic’ variabilities are random in nature and are so great that new circuit analysis techniques are needed which adopt a statistical treatment of the variability of device performances. Monte Carlo (MC) based statistical techniques aim to do this by analysing many randomized copies of the circuit. The randomization can take into account correlation between parameters due to both intra-die and inter-die effects. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The use of principal components analysis (PCA) and ‘Statistical Behavioural Circuit Blocks (SBCB)’ is investigated as a means of reducing the dimensionality of the analysis, and this is combined with an implementation of ‘Statistical Blockade (SB)’ to achieve significant reduction in the computational costs. The purpose of SBCBs is to model the most important aspects of the device’s or circuit building block’s behaviour, to an acceptable accuracy, with a relatively small number of parameters. The SB algorithm applies Extreme Value Theory (EVT) to circuit analysis by eliminating randomised parameter vectors that are considered unlikely to produce ‘rare event’ circuits. These circuits are needed for circuit yield failure predictions and occur on the ‘tails’ of Gaussian-like probability distributions for circuit performances. Versions of the circuit analysis program ‘SPICE’ with a Python harness called RandomSPICE are used to produce SBCBs by generating and statistically analysing randomized transistor-level versions of the sub-blocks for which behavioural models are required. The statistical analysis of circuits employing these sub-blocks is achieved by a new MATLAB harness called RandomLA. The computational time savings that may be achieved are illustrated by the statistical analysis of representative circuits. A computation time reduction of 98.7% is achieved for a commonly used asynchronous circuit element. Quasi-Monte Carlo (QMC) analysis with ‘low discrepancy sequences (LDS)’ is introduced for further computation reduction. QMC analysis using SBCB behavioural models with SB is evaluated by applying it to more complex examples and comparing the results with those of transistor level simulations. The analysis of SRAM arrays is taken as a case study for VLSI circuits containing up to 1536 transistors, modeled with parameters appropriate to 35nm technology. Significantly faster statistical analysis is shown to be possible when the aim is to obtain predictions of the yield for fabrication. Saving of up to 99.85% in computation time was obtained with larger circuits.

The thesis is available as PDF (3.1MB).