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APT Advanced Processor Technologies Research Group

Doug Edwards

Senior Lecturer
Room number: IT-2.10
email: douglas.edwards@manchester.ac.uk
Tel.: +44 161 275 6191
Other contact details

Biography

I am a Senior Lecturer in the School of Computer Science. I gained a William Kirtley Entrance Scolarship to study Physics and Electronic Engineering at Manchester University in 1965. After graduating, I received an M.Sc. and Ph.D. for studies of Zinc Sulphide - Silicon Heterojunctions. The object was to produce a blue light emitting diode (Zinc Sulphide having a bandgap of 3.6ev). Alas, the work was many years ahead of its time.

I spent two years as a lecturer in the Electrical Engineering Department at the University of Manchester before moving to Ferranti working on improving the yield of bipolar integrated circuits fabricated using the novel CDI process. I was then appointed to the staff the Computer Science Department in 1975 where I worked on thick film hybrid circuits, high speed optical networks, CAD hardware acclerators, PCB routing software, formal specification of hardware, and latterly design tools for self-timed circuits.

Current Research Interests

My current research interests are in the synthesis of self-timed (asynchronous) circuits. I have directed the Balsa project which has resulted in a freely-available, reliable framework for sythesising large asynchronous systems; in the G3card project, for example, complete ARM compatible processors were described in Balsa, synthesised, fabricated and working silicon received. Currently Balsa research is aimed at significanly improving the performance of generated circuits.

Further work in SEDATE, a collaborative project involving the Universities of Manchester, Newcastle and Edinburgh, is aimed at researching datapath synthesis and test algorithms for variety of self-timed regimes.

Recreational Interests

In my youth, I was an active rock clmber, rugby and cricket player, and walker. I used to be a keen orienteer: crumbling knees have restricted this latter activity to occasional outings. I still get out on my mountain bike when I can find idiots to join me. I am a season ticket holder at MCFC which helps putting life in perspective.

Recent Research Grants

(PI=Principal Investigator, CI=Co-Investigator)
  • EPSRC: EP/D052238/1 "Self-Timed Datapath Synthesis (SEDATE) 2006-2009 (PI)
  • EPSRC: EP/E001947/1 "Meeting the Design Challenges of nano-CMOS electronics" 2006-2010 (CI)
  • EPSRC: GR/S61270/01 (CI) "Advanced Processor Technologies Portfolio Partnership", 2003-2008, (CI)
  • EPSRC: GR/S11084/01 "An Integrated Framework for Formal Verification and Distributed Simulation of Asynchronous Hardware", 2003-2006, (PI)
  • EPRSC: GR/S04314/01 "Visiting Fellowship", 2002-2003 (PI)
  • EU: IST-2002-37796 "Asynchronous Open-Source IP of the DLX Architecture", 2002-2006, (PI)
  • EPSRC: GR/R73867/01 "PLATFORM GRANT - asynchronous logic systems and tools", 2002-2006, (CI)
  • EU: IST-1999-29119 "ACiD3-WG: Asynchronous Working Group", 2000-2004, (PI)
  • EPSRC: GR/N19618 "A Datapath Compiler and Enhanced Simulation Environment for Balsa: An Asynchronous Silicon Synthesis System", 2000-2003, (PI)
  • EPSRC: GR/M40455 "Optimising Balsa: A Synthesis System for Asynchronous Circuits" 1999, (PI)

Some Recent Publications

Links to these publications can be found here
  • E. Tsirogiannis, G. Theodoropoulos, D. Chen, Q. Zhang, L. Janin, D. Edwards, "A Framework for Distributed Simulation for Asynchronous Handshake Circuits", Proceedings 39th Annual Simulation Symposium (ANSS 06), April 2006, (ISBN 0-7695-2559-8.
  • W .B. Toms, D. A. Edwards , A. Bardsley, "Synthesising Heterogeneously Encoded Systems", Proceedings of 12th International Symposium on Asynchronous Circuits and Systems, Grenoble, March 2006 , pp. 138-148, ISBN 0-7695-2498-2 ISSN 1522-8681.
  • Manish Amde, Tomaz Felicijan, Aristides Efthymiou, Douglas Edwards and Luciano Lavagno, "System On Chip; Next Generation Electronics" ( Editor: Bashir Al-Hashimi), Chapter 18, pp 625-656, 2006. IEE Press, ISBN: 0-86341-552-0 & 978-086341-552-4.
  • A Efthymiou, J. Bainbridge and D. Edwards, "Test Pattern Generation and Partial-Scan Methodology for an Asynchronous SoC Interconnect". IEEE Trans VSLI Systems. Vol 13, Issue 12, Dec 2005, pp 1384-1393.
  • L. A. Plana, S. Taylor and D. Edwards , "Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance" Proc ICCD-2005, pp703-710, October, 2005, San Jose, USA ISBN 0-7695-2451-6, ISSN 1063-6404.
  • L. Janin, D. A. Edwards, "Software Visualisation Methods Adapted and Extended for Asynchronous Hardware Design", Proceedings of 9th International Conference on Information Visualisation, July 2005, pp 347-356, ISBN 0-7695-2397-8, ISSN 1550-6037.
  • O. Bamasak, N. Zhang, and D. Edwards, "DiSigncryption: An Integration of Agent-based Signature Delegation with Distributed Reputation Management Scheme", the Proceedings of the 1st International Workshop on Security in Systems and Networks (SNS2005) held in conjunction with IEEE IPDPS2005, April 4-8, 2005, Denver, Colorado, USA.ISBN 0-7695-2312-9, ISSN 1530-2075.
  • M Amde, A Efthymiou, T Felicijan, D Edwards and L Lavagno, Ò Asynchronous On-Chip NetworksÓ IEE CDT, March 2005, pp 273-283, ISSN:1350-2387.
  • W. B. Toms, D. A. Edwards ÒEfficient Synthesis of Speed Independent Combinational Logic CircuitsÓ. Proc 10th Asia and South Pacific Design Automation Confererence (ASP-DAC), Shanghai Jan 2005, pp 1022-1026, IEEE Computer Society. ISBN 0-7803-8736-8.
  • N.Gupta, D. A.Edwards, "Synthesis of Asynchronous Circuits using Early Data Validity", Proc VLSI Design 2005, 18th International Conference on VLSI Design, Kolkata, Jan 2005, pp. 799-803, IEEE Computer Society, ISBN 0-7695-2264-5, ISSN 1063-9667.
  • A Efthymiou, J. Bainbridge and D. Edwards, "Adding Testability to an Asynchronous Interconnect for Globally-Asynchronous, Locally-Synchronous Systems-on-Chip", Proc. IEEE Asian Test Symposium , Taiwan, pp 20-23, Nov 2004, ISBN 0-7695-2235-1.
  • A. Efthymiou, D. Edwards, and C. Sotiriou, "Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits" Proceedings 2004 Design, Automation and Test in Europe (DATE 2004), pp. 672-673, Feb 2004, SBN: 0-7695-2085-5.
  • Lilian Janin, A. Bardsley, D. Edwards, "Simulation and Analysis of Synthesised Asynchronous Circuits", International Journal of Simulation Systems, Science and Technology, Vol 4, No3-4, pp. 31-43, Sept 2003, I SSN: 1473-8031.
  • W. J. Bainbridge, W. Toms, D. Edwards, S. Furber, " Delay Insensitive, Point to Point Interconnect using n-of-m Codes" ,Proceedings of 9th International Symposium on Asynchronous Circuits and Systems, Vancouver, May 2003, pp 132-140, ISBN 0769518982.
  • T. Chelcea, A Bardsley, D. Edwards, S. N. Nowick, "A Burst-Mode Oriented Back-End for the Balsa Synthesis System", Proceedings 2002 Design, Automation and Test in Europe (DATE 2002), pp. 330-337, March 2002, ISBN 0-7695-1471-5.
  • D. Edwards, A. Bardsley, "Balsa: An Asynchronous Hardware Synthesis LanguageÓ, The Computer Journal, vol 45, no 1, pp. 12-18, Jan 2002.
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