Wei Song (宋威)

Research Associate

Project: Globally asynchronous elastic logic synthesis (PI: Dr. Jim Garside)
Room number: IT-302
E-mail: songw@cs.man.ac.uk

Research areas:

  * Synthesis of asynchronous circuits(current project)
  * Asynchronous networks-on-chip
    (PhD, thesis: Spatial Parallelism in the Routers of Asynchronous On-Chip Networks, supervised by Dr. Doug Edwards)
  * Embedded systems and industrial networks (Master)
  * VLSI and FPGA designs (Master and undergraduate)

Extra links:

  * CV (updated on January 2014)
  * Publication
  * My open sourced projects:
    AVS asynchronous Verilog synthesiser (github) in progress
    ASDM-Noc asynchronous SDM NoC (OpenCores, sourceforge)
    vpreproc Verilog macro preprocessor in C++ (github, sourceforge)
    C++/Tcl a C++ interface to handle embedded Tcl interpresters (github)
  * My personal Chinese blog


   "Stupid is as stupid does." --Forrest Gump