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Power, Delay and Area Efficient Self-Timed Multiplexer and Demultiplexer Designs

P. Balasubramanian and D.A. Edwards


Efficient gate level design methods for robust self-timed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters.

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