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APT Group Papers


  1. Wei Shao and Linda Brackenbury
    No-Handshake Asynchronous Survivor memory Unit for a Viterbi Decoder
    Proceedings of 14th International Conference on Electronics, Circuits and Systems, ICECS 2007
    Marrakech, Morocco, December 2007
    ISBN: 1-4244-1378-8
    DOI-Link Abstract PDF (535K) IEEE Copyright
  2. Mohammed A. Abutheraa and David Lester
    Computable Function Representation Using Effective Chebyshev Polynomial
    Proceeding of the 4th Computational and Mathematical Science and Engineering Conference, Italy, 2007
    ISSN 1307-6884
    Abstract Link
  3. C. Kirkham
    Ranked reservoir sampling: an extension to the reservoir sampling algorithm,
    Software - Practice and Experience, Vol 37, issue 12 (Oct. 2007), pp 1285-1288
    ISSN 0038-0644, DOI: 10.1002/spe.v37:12
    DOI-Link Abstract
  4. Jeremy Singer, Gavin Brown, Ian Watson and John Cavazos
    Intelligent selection of application-specific garbage collectors
    Proceedings of the 6th International Symposium on Memory Management 2007,
    pp 91-102, Montreal, Quebec, Canada.
    ISBN : 978-1-59593-893-0
    DOI DOI-Link
    Abstract PDF (145K)
    (c) ACM 2007. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in ISMM '07.
  5. Mikel Lujan, Phyllis Gustafson, Michael Paleczny and Christopher A. Vick
    Speculative Parallelization - Eliminating the Overhead of Failure.
    Proceedings of the International Conference on High Performance Computing and Communications
    - HPCC 2007, pp 460-471.
    ISBN 978-3-540-75443-5, ISSN 0302-9743 (Print) 1611-3349 (Online)
    DOI-Link Abstract
  6. L. A. Plana, D. Edwards, S. Taylor, L. A. Tarazona, A. Bardsley
    Performance-driven syntax-directed synthesis of asynchronous processors
    Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, pp. 43 - 47, Salzburg, Austria, ACM Press, September 2007
    Abstract DOI-Link
  7. L.A Plana, S.B. Furber, S. Temple, M. Khan, Y. Shi, J. Wu, S. Yang
    A GALS Infrastructure for a Massively Parallel Multiprocessor
    IEEE Design & Test of Computers, Volume: 24 , Issue: 5, pp. 454 - 463, Sept.-Oct. 2007
    Digital Object Identifier: 10.1109/MDT.2007.149
    ISSN : 0740-7475
    DOI-Link Abstract PDF (871K) IEEE Copyright
  8. Ian Watson, Chris Kirkhan and Mikel Luján
    A Study of a Transactional Parallel Routing Algorithm
    Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques - (PACT 2007), Brasnov, Romania, Sept. 2007, pp 388-398.
    ISBN: 978-0-7695-2944-8; ISSN: 1089-795X Digital Object Identifier: 10.1109/PACT.2007.4336228
    Abstract PDF (942K) IEEE Copyright
  9. Lilian Janin, Doug Edwards
    CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse
    Lecture Notes in Computer Science, Volume 4707/2007 pp 154-168
    Computational Science and Its Applications, ICCSA August 2007, Springer Berlin / Heidelberg.
    ISBN 978-3-540-74482-5, ISSN 0302-9743
    Abstract Springer Link
  10. Lilian Janin, Doug Edwards
    Speeding Up Verilog Gate-Level Simulation with Bi-Partitioning
    Proceeding of the 6th EUROSIM Congress on Modelling and Simulation, (EUROSIM 2007)
    ISBN 978-3-901608-32-2, ISSN 3-901608-32-X
    Abstract PDF (498K)
  11. Jeremy Singer and Gavin Brown and Mikel Luján and Ian Watson
    Towards Intelligent Analysis Techniques for Object Pretenuring
    Proceedings of the 5th International Conference on Principles and Practice of Programming in Java,
    pp 203-208, Sept. 2007.
    (c) ACM, 2007. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in PPPJ '07.
    ISBN: 978-1-59593-672-1
    Abstract PDF (98K)
  12. J. Zhao, M. Horsnell, I. Rogers, A. Dinn, C. Kirkham, I. Watson
    Optimizing Chip Multiprocessor Work Distribution using Dynamic Compilation
    Euro-Par , IRISA/ENS Cachan, Rennes, France, 28-31 August 2007
    ISBN: 978-3-540-74465-8 , ISSN: 0302-9743 (Print) 1611-3349 (Online)
    DOI-Link Abstract PDF(Preprint) (221K)
  13. L.E.M.Brackenbury, W.Shao
    Lowering power in an experimental RISC processor
    Microprocessors and Microsystems, Vol. 31, No. 5, pp 360-368, Aug 2007.
    ISSN 0141-9331
    Abstract DOI-Link
  14. W. Suntiamorntut, L. E. M. Brackenbury and J. Garside
    Design and implementation of an energy efficient, parallel, asynchronous DSP
    Proceedings of 22nd International Technical Conference on Circuits/Systems, Computers and Communications, (ITC-CSCC), Busan, Korea, July 2007, Vol. 2, pp. 757-758.
    Abstract PDF (74K)
  15. Steve Furber and Steve Temple
    Neural systems engineering
    Journal of The Royal Society Interface 4(13), pp 193-206, April 2007
    ISSN: 1742-5689(Paper) 1742-5662 (Online)
    Abstract DOI-Link
  16. P. Balasubramanian, D.A. Edwards & C. Hari Narayanan
    Low power synthesis of XOR-XNOR intensive combinational logic
    Proc. 20th IEEE Canadian Conference on Electrical and Computer Engineering,
    (CCECE 2007), pp. 234-246, Vancouver, April 2007.
    ISBN 1-4244-1021-5
    DOI-Link Abstract PDF (K) IEEE Copyright
  17. P. Balasubramanian & D.A. Edwards
    Synthesis of Power and Delay optimized NIG structures
    Proc. 20th IEEE Canadian Conference on Electrical and Computer Engineering
    (CCECE 2007), pp. 239-242, Vancouver, April 2007.
    ISBN 1-4244-1021-5
    DOI-Link Abstract PDF (K) IEEE Copyright
  18. B. Sen and S. Furber
    Maximising Information Recovery from Rank-Order Codes
    Proc. SPIE Defense and Security Symposium, Orlando, Florida, 9-13 April 2007.
    ISBN 9780819466921
    Abstract PDF (K) SPIE URL
  19. S.B. Furber, G. Brown, J. Bose, J.M. Cumpstey, P. Marshall and J.L. Shapiro
    Sparse Distributed Memory using Rank-Order Neural Codes
    IEEE Transactions on Neural Networks, Volume 18, Issue 3, May, 2007 pp.648-659
    Digital Object Identifier 10.1109/TNN.2006.890804
    ISSN 1045-9227
    DOI-Link Abstract PDF (1390K) DOI - IEEE Copyright
  20. A. Robinson and J.D. Garside
    Sensitive Registers: a Technique for Reducing the Fetch Bandwidth in Low-Power Microprocessors
    Proceedings of the 17th Great lakes symposium on VLSI (GLSVLSI)
    Pages: 138 - 143, ACM Press, New York, USA, March, 2007.
    Abstract DOI Link
  21. J. Singer and G. Brown and I. Watson
    Branch Prediction with Bayesian Networks
    pp: 96-112, Workshop on Statistical and Machine Learning approaches applied to Architectures and Compilation
    Ghent, Belgium, January, 2007.
    ISBN 978-90-382-1060-5
    Abstract URL
  22. Marc Daumas, David Lester
    Stochastic Formal Methods: An Application to Accuracy of Numeric Software
    p. 262b, 40th Annual Hawaii International Conference on System Sciences (HICSS'07), January 2007.
    E-ISBN 0-7695-2755-8 , ISSN 1530-1605
    Abstract PDF (217K) DOI - IEEE Copyright
2006 papers
Pre-2006 papers