APT Group Papers

This document contains references and links to abstracts for APT group papers in reverse chronological order. Most of these papers are available as PDF/Postscript from here.

2005, 2004, 2003, 2002, 2001, 2000, 1999, 1998, 1997, 1996, 1995, 1994, 1993, 1992

2005

1. Jisheng Zhao; Rogers I. Kirkham, C. Watson, I.
   Loop Parallelisation for the Jikes RVM
   Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, 2005. PDCAT 2005. pp.35-39
   ISBN 0-7695-2405-2
   Abstract PDF (245K) IEEE Copyright
2. Efthymiou A. Bainbridge J. Edwards D.
   Test Pattern Generation and Partial-Scan Methodology for an Asynchronous SoC Interconnect
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
   Volume:13, Issue:12, pp.1384-1393, Dec. 2005.
   ISSN 1063-8210
   DOI Link Abstract PDF (1583K) IEEE Copyright
3. Steve Furber and John Bainbridge
   Future Trends in SoC Interconnect
   Proceedings 2005 International Symposium on System-on-Chip, pp183-186,
   November 2005, Tampere, Finland
   ISBN 0-7803-9294-9, ISSN
   DOI Link Abstract PDF (577K) IEEE Copyright
4. L.A. Plana, S. Taylor and D. Edwards
   Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance
   Proceedings IEEE International Conference on Computer Design ICCD-2005, pp703-710, October, 2005, San Jose, USA
   ISBN 0-7695-2451-6, ISSN 1063-6404
   DOI Link Abstract PDF (287K) IEEE Copyright
5. S. Nooshabadi, J. Garside
   Teaching Embedded Systems Design An International Collaborative Project
   Proceedings 35th ASEE/IEEE Frontiers in Education Conference, Indianapolis, October 19-22, 2005
   DOI 10.1109/FIE.2005.1612049
   ISBN :
   Abstract PDF (1538K) IEEE Copyright
6. Jeremy Singer
   Concept Assignment as a Debugging Technique for Code Generators
   Fifth IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2005), pp.75-84, Budapest, Hungary, September 2005
   ISBN 0-7695-2292-0
   Abstract PDF (230K) IEEE Copyright
7. Yijun Liu and Steve Furber
   The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics
   Lecture Notes in Computer Science, Volume 3728 / 2005, pp.647-656, Springer-Verlag GmbH
   ISSN: 0302-9743
   Proceedings Integrated Circuit and System Design: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 20-23, 2005. Editors: Vassilis Paliouras, Johan Vounckx, Diederik Verkest
   ISBN: 3-540-29013-3; DOI: 10.1007/11556930_66
   Abstract PDF(SpringerLink)
8. J. Bose, S.B. Furber, J.L. Shapiro.
   A spiking neural sparse distributed memory implementation for learning and predicting temporal sequences.
   Lecture Notes in Computer Science, Volume 3696 / 2005, pp.115-120, Springer-Verlag GmbH
   ISSN: 0302-9743
   Proceedings ICANN 2005 (International Conference on Artificial Neural Networks, September 11-15, 2005, Warsaw, Poland)
   DOI Link ISBN 3-540-28752-3, DOI: 10.1007/11550822_19
   Abstract PDF(SpringerLink)
9. Cesar Munoz, David Lester
   Real Number Calculations and Theorem Proving
   Theorem Proving in Higher Order Logics, 18th International Conference, TPHOLs 2005, Oxford, UK, August 22-25, 2005, Proceedings, editors: Joe Hurd and Thomas F. Melham
   Lecture Notes in Computer Science, Volume: 3603, pp.195-210.
   ISBN 3-540-28372-2
   Abstract DOI Link
10. J. Bose, S.B. Furber, J.L. Shapiro.
    An associative memory for the on-line recognition and prediction of temporal sequences.
    International Joint Conference on Neural Networks, (IJCNN), August 2005, Montreal, Canada.
    ISBN 0-7803-9049-0
    DOI Link Abstract PDF (92K) IEEE Copyright
11. Ian Rogers, Jisheng Zhao, Chris Kirkham, Ian Watson
    An Automatic Runtime DOALL Loop Parallelisation Optimization for Java
    European Conference on Object-Oriented Programming Workshop on Parallel/High-Performance Object-Oriented Scientific Computing (POOSC'05), Glasgow, UK, July 25, 2005
    ISBN , ISSN
    Abstract PDF (355K)
12. Ian Rogers, Chris Kirkham
    JikesNODE and PearColator: A Jikes RVM Operating System and Legacy Code Execution Environment
    European Conference on Object-Oriented Programming Workshop on Programming Languages and Operating Systems (ECOOP-PLOS'05), Glasgow, UK, July 26, 2005.
    ISBN , ISSN
    Abstract PDF (230K)
9999
13. A. Efthymiou, J.D. Garside, I.Papaefstathiou,
    A Low-Power Processor Architecture Optimized for Wireless Devices
    Proceedings of 16th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2005), Samos, Greece, July 23-25, 2005, pp 185-190.
    ISSN: 1063-6862
    DOI-Link Abstract PDF (241K) IEEE Copyright
14. Lirong He, Lisha He, Ian Rogers
    New Security Protocol For M-Learning
    IADATe-2005 International Confernece on Education, Biarritz, France, July 7-9, 2005
    ISBN , ISSN
    Abstract PDF (77K)
15. Lirong He, Ian Rogers, Lisha He
    A New Real-Time Multimedia Control Protocol For Distance Learning
    IADATe-2005 International Confernece on Education, Biarritz, France, July 7-9, 2005
    ISBN , ISSN
    Abstract PDF (139K)
16. Lilian Janin and Doug Edwards,
    Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design.
    9th International Conference on Information Visualisation, July 2005, London. pp 347-356
    ISBN 0-7695-2397-8, ISSN 1550-6037
    DOI-Link Abstract PDF (611K)
17. J. Bose, S.B. Furber, J.L. Shapiro.
    A system for transmitting a coherent burst of activity through a network of spiking neurons.
    Accepted for: WIRN 2005 ( XVI ITALIAN WORKSHOP ON NEURAL NETWORK, Vietri Sul Mare, Italy, June 8-11, 2005)
    ISBN , ISSN
    DOI-Link Abstract PDF (249K)
18. Yijun Liu, Steve Furber
    A low power embedded dataflow coprocessor.
    Proceedings Annual Symposium on VLSI, May 2005, Tampa, Florida, USA. pp 246-247.
    ISBN 0-7695-2365-X.
    Abstract PDF (88K) IEEE Copyright
19. S B Furber
    Future Trends in SoC Interconnect
    Proc. IEEE International Symposium on Design, Automation and Test (VLSI-TSA-DAT), Hsinchu, Taiwan, April 27-29 2005, pp. 290-293. Keynote talk.
    ISBN 0-7803-9060-1, ISSN
    DOI-Link Abstract PDF (239K) IEEE Copyright
20. O. Bamasak, N. Zhang, and D. Edwards,
    "DiSigncryption: An Integration of Agent-based Signature Delegation with Distributed Reputation Management Scheme"
    Proceedings of the 1st International Workshop on Security in Systems and Networks (SNS2005) (Held in conjunction with 19th IEEE International Parallel and Distributed Processing Symposium), April 2005, Denver, Colorado, USA. pp 293.
    ISBN 0-7695-2312-9, , ISSN 1530-2075,
    DOI-Link Abstract PDF (168K) IEEE Copyright
21. M Amde, A Efthymiou, T Felicijan, D Edwards and L Lavagno
    Asynchronous On-Chip Networks
    IEE CDT Volume 152, Issue 02, March 2005, pp 273-283.
    ISSN:1350-2387
    DOI-Link Abstract PDF (313K)
22. W. B. Toms, D. A. Edwards
    Efficient Synthesis of Speed Independent Combinational Logic Circuits.
    Proc 10th Asia and South Pacific Design Automation Confererence (ASP-DAC)
    Shanghai Jan 2005, pp 1022-1026, IEEE Computer Society.
    ISBN 0-7803-8736-8
    DOI-Link Abstract PDF (331K) IEEE Copyright
23. Jisheng Zhao, Ian Rogers, Chris Kirkham
    A System for Runtime Loop Optimisation in the Jikes RVM.
    PREP 2005, Lancaster 2005.
    ISBN , ISSN
    DOI-Link Abstract PDF(266K)
24. C. Brej, J.D.Garside
    A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
    Proc VLSI Design 2005, 18th International Conference on VLSI Design,
    Kolkata, Jan 2005, pp. 368-373, IEEE Computer Society.
    ISBN 0-7695-2264-5, ISSN 1063-9667
    DOI-Link Abstract PDF (144K) IEEE Copyright
25. P. Capewell, I. Watson
    A RISC Hardware Platform for Low Power Java
    Proc VLSI Design 2005, 18th International Conference on VLSI Design,
    Kolkata, Jan 2005, pp. 138-143, IEEE Computer Society.
    ISBN 0-7695-2264-5, ISSN 1063-9667
    DOI-Link Abstract PDF (94K) IEEE Copyright
26. N.Gupta, D. A.Edwards
    Synthesis of Asynchronous Circuits using Early Data Validity
    Proc VLSI Design 2005, 18th International Conference on VLSI Design,
    Kolkata, Jan 2005, pp. 799-803, IEEE Computer Society.
    ISBN 0-7695-2264-5, ISSN 1063-9667
    DOI-Link Abstract PDF (454K) IEEE Copyright

2004

• A Efthymiou, J. Bainbridge and D. Edwards
  Adding Testability to an Asynchronous Interconnect for GALS SoC
  Proc. IEEE Asian Test Symposium, Taiwan, pp 20-23, Nov 2004.
  ISBN 0-7695-2235--1
  DOI-Link Abstract PDF (93K) IEEE Copyright
• T.Felicijan, S.B.Furber
  An Asynchronous On-Chip Network Router with Quality-of-Service (QoS) Support
  Proceedings IEEE International SOC Conference, Santa Clara, CA, Sept. 2004, pp274-277
  ISBN: 0-7803-8445-8.
  Abstract PDF (302K) IEEE Copyright
• W. Suntiamorntut, L.E.M. Brackenbury
  Energy efficient functional unit for a compute-intensive asynchronous DSP
  The Embedded Systems Show (ESS2004), Birmingham, 13-14 October 2004.
  Abstract PDF (182K)
• W. Suntiamorntut, N. Gupta, L.E.M. Brackenbury, J. Garside
  Energy efficient functional unit for a parallel asynchronous DSP
  GSPX:The international embedded solutions event, Sept. 27-30, USA, 2004.
  Abstract PDF (150K)
• S.B. Furber, W.J. Bainbridge, J.M. Cumpstey and S. Temple
  A Sparse Distributed Memory based upon N-of-M Codes
  Neural Networks Vol: 17/10 pp 1437-1451. Dec. 2004
  Abstract DOI (445K) Copyright ©2004 Elsevier.
  
• Y. Liu and S.B. Furber
  The Design of a Low-Power Asynchronous Multiplier
  Proceedings of the 2004 International Symposium on Low Power Electronics and Design, ISLPED'04. pp 301-306.
  ISBN 1-58113-929-2
  Abstract PDF (127K)
• Y. Liu and S.B. Furber
  Minimizing the Power Consumption of an Asynchronous Multiplier
  Integrated Circuit and System Design - Power and Timing Modeling, Optimization and Simulation
  14th International Workshop, PATMOS 2004, Greece, Sept. 2004, Proceedings.
  pp. 289-300, LNCS 3254, Springer.
  ISSN 0302-9743; ISBN 3-540-23095-5
  Abstract PDF (286K)
• A. Yakovlev, S.B. Furber, R. Krenz, A. Bystrov
  Design and Analysis of a Self-Timed Duplex Communication System
  IEEE Transactions on Computers, Vol. 53 no. 7, July 2004, pp. 798-814
  ISSN 0018-9340.
  DOI Abstract PDF (1758K). IEEE Copyright
• A. Efthymiou, W. Suntiamorntut, J.D. Garside, L.E.M. Brackenbury
  An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
  Proceedings of the 10th IEEE Intl Symp. on Asynchronous Circuits and Systems (ASYNC'04),
  pp. 207-215, Crete, Apr. 2004
  ISBN 0-7695-2133-9, ISSN 1522-8681.
  DOI-Link Abstract PDF (97K). IEEE Copyright
• A. Efthymiou, J.D. Garside
  A CAM with mixed serial-parallel comparison for use in low energy caches
  IEEE Transactions on VLSI Systems, Vol. 12, no. 3, Mar. 2004, pp 325 - 329
  ISSN 1063-8210
  DOI-Link Abstract PDF (248K). IEEE Copyright
• W.J.Bainbridge, L.A.Plana, S.B.Furber
  The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip
  Proceedings of the Design, Automation and Test in Europe Conference and Exhibition,
  Designers' Forum (DATE'04), Volume 3, p. 274, Paris, Feb 2004
  ISBN 07695-2085-5
  DOI-Link Abstract PDF (347K) IEEE Copyright
• A. Efthymiou, C. Sotiriou, D.A. Edwards
  Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits
  Proceedings of the Design, Automation and Test in Europe Conference and Exhibition,
  Volume I (DATE'04), p. 672, Paris, Feb. 2004
  ISBN 07695-2085-5
  DOI-Link Abstract PDF (35K). IEEE Copyright

2003

• L. Janin, A. Bardsley and D. A. Edwards
  Simulation and Analysis of Synthesised Asynchronous Circuits
  International Journal of Simulation Systems, Science & Technology, Vol. 4, No. 3-4, pp. 31-43
  ISSN 14738031
  Abstract PDF (234K).
• T. Felicijan, S.B. Furber
  An Asynchronous Ternary Logic Signalling System
  IEEE Transactions on VLSI Systems, Vol. 11, no. 6, Dec. 2003, pp 1114 - 1119
  ISSN 1063-8210
  Abstract PDF (365K). IEEE Copyright
• T. Felicijan, W.J. Bainbridge, S.B. Furber,
  An asynchronous low latency arbiter for Quality of Service (QoS) applications.
  15th IEEE International Conference on Microelectronics (ICM'03), pp 123-126,
  Cairo, Egypt, Dec 2003
  ISBN: 977-05-2010-1
  DOI-Link Abstract PDF (74K). IEEE Copyright
• S. Mohammadi, S.B. Furber and J.D. Garside
  Designing Robust Asynchronous Circuits
  IEE Proceedings - Circuits, Devices and Systems, vol. 150 no. 3, June 2003, pp. 161-166.
  ISSN 1350-2409.
  DOI-Link Abstract PDF (445K).
• T.Felicijan, S.B.Furber
  Quality of Service (QoS) for Asynchronous On-Chip Networks
  Formal Methods for Globally Asynchronous Locally Synchronous Architecture (FMGALS 2003)
  Pisa, Italy, Sept. 2003
  Abstract PDF (74K).
• D.Hormdee, J.D.Garside, S.B.Furber
  An asynchronous copy-back cache architecture
  Microprocessors and Microsystems Vol.27 Iss.10 pp 485-500 Nov 2003
  ISSN 0141-9331
  DOI-Link Abstract Microprocessors and Microsystems Vol:27, Iss.10 © 2005 Elsevier B.V.
• D. R. Lester and P.Gowland
  Using PVS to validate the Algorithms of an Exact Arithmetic
  Theoretical Computer Science, Volume 291; pp203-218, Jan 2003.
  Abstract Theoretical Computer Science Vol:291, Iss.2 © 2005 Elsevier B.V.
• X. Ni, W. Suntiamorntut, B.M.G. Cheetham, L.E.M. Brackenbury and D.J. Tait
  Design of asynchronous function unit & software development tools for a low-power DSP
  IEE Colloquium on DSP_enabled Radio, pp 1-10; Scotland; Sept 2003 DOI-Link
• C.F. Brej and J.D. Garside
  Early Output Logic using Anti-Tokens
  Proceedings International Workshop on Logic Synthesis
  IEEE/ACM Publications, May 2003; pp. 302-309
  Abstract PDF(123K) Presentation slides (209K PowerPoint) IEEE Copyright
• W. Suntiamorntut, L. Brackenbury
  Functional Unit for Low-Power DSP Architecture
  Proceedings IEE Postgraduate Seminar on SoC Design, Test and Technology
  IEE Publications, September 2003
  ISSN 0963-3308
• L. Ren, P. Marshall, S.B. Furber
  Prototyping a Digital Neural Network System-on-Chip using an Altera Excalibur Device
  Proceedings IEE Postgraduate Seminar on SoC Design, Test and Technology
  IEE Publications, September 2003
  ISSN 0963-3308
  Abstract PDF (138K). © IEE Publications.
• Y. Liu, S.B. Furber
  A Low-Power Asynchronous Multiplier
  Proceedings IEE Postgraduate Seminar on SoC Design, Test and Technology
  IEE Publications, September 2003
  ISSN 0963-3308
• L.A. Plana, P.A. Riocreux, W.J. Bainbridge, A. Bardsley, S. Temple, J.D. Garside, Z.C. Yu,
  SPA - A Secure Amulet Core for Smartcard Applications
  Microprocessors and Microsystems Vol. 27, Issue 9; pp. 431-446
  October 2003
  ISSN 0141-9331
  DOI-Link Abstract Microprocessors and Microsystems Vol:27, Iss.9 © 2005 Elsevier B.V.
• Z.C. Yu, S.B. Furber, L.A. Plana
  An Investigation into the Security of Self-timed Circuits
  Proceedings of the 9th IEEE Intl Symp. on Asynchronous Circuits and Systems (ASYNC'03),
  pp 206-215, Vancouver, May 2003
  ISBN 0-7695-1898-2, ISSN 1522-8681
  Abstract PDF (660K). IEEE Copyright
• A. Efthymiou, J.D. Garside
  Adaptive Pipeline Structures for Speculation Control
  Proceedings of the 9th IEEE Intl Symp. on Asynchronous Circuits and Systems (ASYNC'03),
  pp. 46-55, Vancouver, May 2003
  ISBN 0-7695-1898-2 ISSN 1522-8681
  DOI-Link Abstract PDF (344K). IEEE Copyright
• W.J. Bainbridge, W.B. Toms, D.A. Edwards, S.B. Furber,
  Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes
  Proceedings of the 9th IEEE Intl Symp. on Asynchronous Circuits and Systems (ASYNC'03),
  pp. 132-140, Vancouver, May 2003
  ISBN 0-7695-1898-2 ISSN 1522-8681
  DOI-Link Abstract PDF (297K). IEEE Copyright
• J.D. Garside
  A Microcomputer Interfacing Laboratory
  International Journal of Electrical Engineering Education Vol. 40 Issue 1 pp.13-26, January 2003
  ISSN 0020-7209
  Abstract PDF (88K).

2002

• D. R. Lester, S. Chambers and H. L. Lu;
  A Constructive Algorithms for finding the Exact Roots of Polynamials with Computable Real Coefficients
  Theoretical Computer Science, Volume: 279; pp 51-64; 01-JAN-02.
  Abstract Theoretical Computer Science Vol: 279, Iss.1-2 © 2005 Elsevier B.V.
• W.J.Bainbridge, S.B.Furber
  CHAIN: A Delay Insensitive CHip Area INterconnect
  IEEE Micro special issue on Design and Test of System on Chip
  Vol:22, Iss:5, September/October 2002, pp16-23
  ISSN 0272-1732
  Abstract PDF (290K). IEEE Copyright
• A. Efthymiou, J.D. Garside
  Adaptive Pipeline Depth Control for Processor Power-Management
  Proceedings of ICCD'02, pp. 454-457
  Freiburg, September 2002
  ISBN 0-7695 1700-5; ISSN 1063-6404
  DOI-Link Abstract PDF (266K). IEEE Copyright
• D. Hormdee, J.D. Garside, S.B. Furber
  An Asynchronous Victim Cache
  Proceedings Euromicro Symposium on Digital System design2. Dortmund, September 2002
  ISBN: 0-7695-1790-0
  DOI-Link Abstract PDF (407K). IEEE Copyright
• A. Efthymiou, J.D. Garside
  An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks
  Proceedings of ISLPED'02, pp.136-141
  Monterey, August 2002
  ISBN 1-58113-475-4
  DOI-Link Abstract PDF (152K).
• M. Lewis and L. Brackenbury
  CADRE: an Asynchronous Embedded DSP for Mobile Phone Applications
  Design Automation for Embedded Systems, Vol. 6, No. 4, pp.451-475; July 2002.
  ISSN 0929-5585
  Abstract D.A.E.S © Kluwer
• L.A. Plana, P.A. Riocreux, W.J. Bainbridge, A. Bardsley, J.D. Garside, S. Temple
  SPA - A Synthesisable Amulet Core for Smartcard Applications
  Proceedings of Async'2002, pp. 201-210
  Manchester, April 2002.
  ISBN 0-7695-1540-1, ISSN 1522-8681
  Abstract PDF (107K). IEEE Copyright
• T. Chelcea, A. Bardsley, D. A. Edwards, S. M. Nowick
  A Burst-Mode Oriented Back-End for the Balsa Synthesis System
  Proceedings of DATE '02, pp. 330-337
  Paris, March 2002
  ISBN 07695-1471-5, ISSN 1530-1591
  Abstract PDF (150K). IEEE Copyright
• S. B. Furber
  Validating the AMULET Microprocessors
  The Computer Journal vol.45 No.1 BCS pp.19-26 2002, Published OUP.
  (based on material from the Banff'99 workshop in Ullapool, September 1999)
  ISSN 0010-4620
  Abstract PDF From OUP site (194K)
• Doug Edwards, Andrew Bardsley
  Balsa: An Asynchronous Hardware Synthesis Language
  The Computer Journal vol.45 No.1 BCS pp.12-18, Published OUP.
  (based on material from the Banff'99 workshop in Ullapool, September 1999)
  ISSN 0010-4620
  Abstract PDF From OUP site (126K)

2001

• D. Hormdee and J. Garside
  An Asynchronous Copy-Back Cache Architecture
  in proceedings of PREP 2001, 9-11 April 2001
• I. Rogers
  A Dynamic Binary Translator in a Java Environment
  in proceedings of PREP 2001, 9-11 April 2001
  Abstract PDF (168K).
• P. Gowland and D. R. Lester
  A Survey of Exact Arithmetic Implementations
  in proceedings Computability and Complexity in Analysis, Editors: J. Blanck, V. Brattka and P. Hertling; pp 30-47; LNCS; Volume: 2064 Springer Verlag 01-APR-01.
  ISSN: 0302-9743
  Abstract ( LNCS 2064). Springer, 2001. (© Springer-Verlag)
• D.R.Lester
  Effective Continued Fractions
  in proceedings 15th IEEE Symposium on Computer Arithmetic; pp 63-170 Editors: N. Burgess and L. Ciminiera, IEEE Computer Society Press 01-JUN-01.
  Abstract PDF (627K). IEEE Copyright
• J.Sargeant, C.Kirkham and I.Watson
  Editors: M. Mohnen, P. P and K. Koopman
  Exploiting Implicit Parallelism in Functional Programs with SLAM
  Implementation of Functional Languages, 12th International Workshop, IFL 2000
  Lecture Notes in Computer Science; ISBN: 3540419195; ISSN:03029743
  pp 19-36; Springer Verlag; Vol: 2011 01-JAN-01
  Abstract ( LNCS 2011). Springer, 2001. (© Springer-Verlag)
• M. Lewis and L. Brackenbury
  Low power asynchronous DSP for digital mobile phones
  IEE Seminar on Low Power IC Design.
  IEE Press; ISSN: 09633308; pp 13/1-13/6; London; JAN-200
  Abstract PDF (594K). © IEE Publications.
• L.Brackenbury, M. Cumpstey, S. Furber and P. Riocreux
  Applying asynchronous techniques to a Viterbi decoder design
  IEE Seminar on Low Power IC Design.
  IEE Press ISSN: 09633308; pp 2/1-2/5; London; JAN-2001
  Abstract PDF (394K). © IEE Publications.
• D. Donaghy, L. Brackenbury and S. Hall
  Combining SOI Technology and Asynchronous Design Techniques for Power Reduction
  Electrochemical Society; Proceedings 10th International Symposium on Silicon-on-Insulator Technology and Devices. 199th Meeting of Electrochemical Society, Washington DC, USA
  MAR-2001;pp 337-342
• D. Donaghy, L. Brackenbury and S. Hall
  A simulation study to quantify the advantages of silicon-on-insulator (SOI) technology for low power
  IEE Seminar on Low Power IC Design.
  IEE Press; ; London; ISSN: 09633308; pp11/1-11/6; JAN-2001;
  Abstract PDF (527K). © IEE Publications.
• M. Lewis, L.E.M. Brackenbury
  CADRE: A Low-Power, Low-EMI DSP Architecture for Digital Mobile Phones
  VLSI Design special issue on low power system design, Vol. 12, No. 3, pp. 333-348, September 2001
  Abstract PDF (161K).
• A. Efthymiou, J.D. Garside, S. Temple
  A Comparative Power Analysis of an Asynchronous Processor
  Proceedings PATMOS'01 pp. 10.1.1-10
  Yverdon-les-bains, Switzerland, September 2001
• Abstract PDF (134K).
• G. Theodoropoulos, D.A. Edwards
  Towards a Framework for the Distributed Simulation of Asynchronous Hardware
  UKSIM2001: Conference on Computer Simulation 2001
  Cambridge, UK, March 2001
  Abstract PDF (124K).
• S. B. Furber, A. Efthymiou, J.D. Garside, M.J.G. Lewis, D.W. Lloyd and S. Temple
  Power Management in the AMULET Microprocessors
  IEEE Design and Test of Computers Journal, special issue, Vol:18, Iss.2, pp. 42-52 (Ed. E. Macii),
  March-April 2001
  ISSN: 0740-7475
  DOI-Link Abstract PDF (752K). IEEE Copyright
• D. Hormdee, J.D. Garside
  AMULET3i Cache Architecture
  Proceedings Async 2001 pp. 152-161 IEEE Computer Society Press
  March 2001
  (ISSN 1522-8681 ISBN 0-7695-1034-4)
  Abstract PDF (956K). IEEE Copyright
• W.J. Bainbridge, S. Furber
  Delay Insensitive System-on-Chip Interconnect Using 1-of-4 Data Encoding
  Proceedings Async 2001 pp. 118-126 IEEE Computer Society Press
  March 2001
  (ISSN 1522-8681 ISBN 0-7695-1034-4)
  Abstract PDF (644K). IEEE Copyright
• D.W. Lloyd, J. D. Garside
  A Practical Comparison of Asynchronous Design Styles
  Proceedings Async 2001 pp. 36-45 IEEE Computer Society Press
  March 2001
  (ISSN 1522-8681 ISBN 0-7695-1034-4)
  Abstract PDF (876K). IEEE Copyright
• P.A. Riocreux, L.E.M. Brackenbury, M. Cumpstey, S.B. Furber
  A Low-Power Self-Timed Viterbi Decoder
  Proceedings Async 2001 pp. 15-24 IEEE Computer Society Press
  March 2001
  (ISSN 1522-8681 ISBN 0-7695-1034-4)
  Abstract PDF (880K). IEEE Copyright
• M. Lewis, L. Brackenbury
  Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank
  Proceedings Async 2001 pp. 4-14 IEEE Computer Society Press
  March 2001
  (ISSN 1522-8681 ISBN 0-7695-1034-4)
  Abstract PDF (824K). IEEE Copyright
• Ahmed El-Mahdy and Ian Watson.
  A two dimensional vector architecture for multimedia.
  In the Proceedings of the European Conference on Parallel Computing, Euro-Par 2001.
  Lecture Notes in Computer Science, pp.687-696, Volume 2150, Springer Verlag, 2001.
  ISSN: 0302-9743
  Abstract ( LNCS 2150). Springer, 2001. (© Springer-Verlag)

2000

• B. Burrows and D.R.Lester
  Exact Arithmetic and the Korteweg-de Vries Equation
  IEEE Computer Society Press, Editor: W. Weierauch; CCA2000 Swansea, 01-SEP-00.
• P. Gowland and D.R.Lester
  The Correctness of an Implementation of Exact Arithmetic
  Editors: M. Muller and B. Bajard; RNC4 Dagstuhl, IEEE Computer Society Press; 01-APR-00.
• P.Gowland and D.R.Lester
  Validating the Correctness of an Exact Arithmetic Package; IMACS
  Editors: S. Dietrich, A. Facins and N. Bierlox; in Proceedings SCAN/INTERVAL 2000; pp 125; 01-SEP-00.
• P. Gowland and D. R. Lester
  Towards a machine-checked congruence for exact arithmetic
  Editor: K. Kulisch; SCAN2000 Karlsruhe, IEEE Computer Society Press; 01-SEP-00.
• A. Bardsley, D. A. Edwards
  Synthesising an asynchronous DMA controller with Balsa
  ISSN: 1383-7621
  Abstract
  Journal of Systems Architecture 46 (2000) pp. 1309-1319
• S. B. Furber and J. Liu
  A Novel Area-Efficient Binary Adder
  Thirty-Fourth Asilomar Conference on Signals, Systems & Computers, 2000
  Volume: 1, pp. 119-123. Pacific Grove, California, USA
  ISSN 1058-6393
  Abstract PDF (456K). IEEE Copyright
• L. Brackenbury and K. Bell
  The Optical Encryption of Digital Data
  Applied Optics, Vol. 39, No. 29, October 2000, pp. 5374-5379,
  Publisher: Optical Society of America, ISSN: 0003-6935
  Abstract PDF (249K). © 2002 OPTICSINFOBASE.ORG
• D. Donaghy, L. Brackenbury and S. Hall
  Exploiting Asynchronous Self-Timed Techniques on SOI Technology for Low Power
  EUROSOI 2000 Workshop, Granada, October 2000, pp.1-4.
  Abstract
• S. B. Furber, D. A. Edwards and J. D. Garside
  AMULET3: a 100 MIPS Asynchronous Embedded Processor
  ICCD'00
  17-20th September 2000
  Abstract PDF (548K). IEEE Copyright
• A. Bardsley, D. A. Edwards
  The Balsa Asynchronous Circuit Synthesis System
  FDL 2000
  4-8th September 2000.
  Abstract PDF (166K).
• J. Garside
  AMULET3i - an Asynchronous System-on-Chip
  HOT Chips 12
  14th-15th August 2000
• S. B. Furber, A. Efthymiou and M Singh
  A Power-Efficient Duplex Communication System
  Proc. AINT'2000 Workshop, Delft, The Netherlands, 19-20 July 2000
  Abstract PDF (74K).
• L. Brackenbury, M. Cumpstey, S. Furber and P. Riocreux
  An Asynchronous Viterbi Decoder
  European Low Power Initiative for Electronic System Design (ESDLPD) Third International Workshop
  July 2000, pp. 8-21. ISBN: 90-5326-036-6. Publisher: DIMES
  Abstract
• W.J. Bainbridge, S.B. Furber
  MARBLE: An Asynchronous On-Chip Macrocell Bus
  Microprocessors and Microsystems Vol.24 No.4 pp.213-222
  1st April 2000
  ISSN 0141-9311
  Abstract Microprocessors and Microsystems(Link to Journal)
  
• S. Temple, S.B. Furber
  On-chip timing reference for self-timed microprocessor
  IEE Electronics Letters Vol.36 No. 11 pp.942-943
  25th May 2000
  ISSN 0013-5194
  Abstract PDF (313K). © IEE 2000.
• S.B. Furber
  Kicking out the Clock
  ISD (Integrated System Design)
  Vol.12 #129 pp.30-38
  May 2000
  ISSN 1080-2797
• M. Lewis, L.E.M. Brackenbury
  A low-power asynchronous DSP architecture for digital mobile phone chipsets
  Proceedings PREP 2000, April 2000
  Abstract PDF (575K).
• M. Lewis, L.E.M. Brackenbury
  An Instruction Buffer for a Low-Power DSP
  Proceedings Async 2000 pp. 176-186 IEEE Computer Society Press
  April 2000
  (ISSN 1522-8681 ISBN 0-7695-0586-4)
  Abstract PDF (120K). IEEE Copyright
• J.D. Garside, W.J. Bainbridge, A. Bardsley, D.M. Clark, D.A. Edwards, S.B. Furber, J. Liu, D.W. Lloyd, S. Mohammadi, J.S. Pepper, O. Petlin, S. Temple, J.V. Woods
  AMULET3i - an Asynchronous System-on-Chip
  Proceedings Async 2000 pp. 162-175 IEEE Computer Society Press
  April 2000
  (ISSN 1522-8681 ISBN 0-7695-0586-4)
  Abstract PDF (220K). IEEE Copyright
• P. A. Riocreux, M. J. G. Lewis, L. E. M. Brackenbury
  Power reduction in self-timed circuits using early-open latch controllers
  IEE Electronics Letters Vol.36 pp.115-116
  January 2000
  ISSN 0013-5194
  Abstract PDF (108K). © IEE 2000.
• Greg Wright, Ahmed El-Mahdy, and Ian Watson.
  Dynamic Java threads on the Jamaica single-chip multiprocessor.
  In Second Annual Workshop on Hardware Support for Objects and Microarchitectures for Java in conjunction with ICCD'00, pages 1-5, Austin, Texas, 2000.
  

1999

• D Owen, A Rawsthorne.
  Consistent Windowing Interfaces in Distributed Heterogeneous Environments.
  Proceedings of the IFIP WG6.1 Second International Working Conference on Distributed Applications and Interoperable Systems (DIAS ' 99) June 28 - July 1, 1999, Helsinki, Finland.
• I Rogers, A Rawsthorne
  Exploiting Hardware Resources: Register Assignment across Method Boundaries
  In Workshop on Hardware Support for Objects and Microarchitectures for Java in conjunction with ICCD'99, pages 27-31, Austin, Texas, 1999.
  Abstract PDF (136K).
• S-H. Chung, S.B. Furber
  The design of the control circuit for an asynchronous instruction prefetch unit using signal transition graphs
  Workshop on Hardware Design and Petri Nets in the 20th Int. Conf. on Application and Theory of Petri Nets, pp. 131-147, 1999, Williamsburg, USA.
  Abstract PDF (142K).
• J.D. Garside, S.B. Furber, S-H. Chung
  AMULET3 Revealed
  Proceedings Async '99 pp. 51-59 IEEE Computer Society Press
  April 1999
  (ISSN 1522-8681 ISBN 0-7695-0031-1)
  Abstract PDF (96K). IEEE Copyright
• D.W. Lloyd, J.D. Garside, D.A. Gilbert
  Memory Faults in Asynchronous Microprocessors
  Proceedings Async '99 pp. 71-80 IEEE Computer Society Press
  April 1999
  (ISSN 1522-8681 ISBN 0-7695-0031-1)
  Abstract PDF (96K). IEEE Copyright
• M. Lewis, J.D. Garside, L.E.M. Brackenbury
  Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
  Proceedings Async '99 pp. 27-35 IEEE Computer Society Press
  April 1999
  (ISSN 1522-8681 ISBN 0-7695-0031-1)
  DOI-Link Abstract PDF (172K). IEEE Copyright
• S.B. Furber, J.D. Garside, P. Riocreux, S. Temple, P. Day, J. Liu, N.C. Paver
  AMULET2e: An Asynchronous Embedded Controller
  Proceedings of the IEEE, volume 87, number 2 (February 1999), pp. 243-256
  ISSN 0018-9219
  Abstract PDF (420K). IEEE Copyright
• I Watson, G Wright, and A El-Mahdy.
  VLSI architecture using lightweight threads (VAULT) - choosing the instruction set architecture.
  In Workshop on Hardware Support for Objects and Microarchitectures for Java in conjunction with ICCD'99, pages 40-44, Austin, Texas, 1999.
  Proceedings PDF (1.52M).

1998

• S-Y. Tan, W-F. Yen and S.B. Furber
  The Design of an Asynchronous VHDL Synthesizer
  Proceedings DATE'98, Paris, February 1998
  Abstract PDF (160K). IEEE Copyright
• W.J. Bainbridge and S.B. Furber
  Asynchronous Macrocell Interconnect using MARBLE
  Proceedings Async'98, IEEE Computer Society Press, April 1998
  Abstract PDF (120K). IEEE Copyright
• S.B. Furber, J.D. Garside, S. Temple, P. Day and N.C. Paver
  Asynchronous Embedded Control
  Journal of Integrated Computer-Aided Engineering, Wiley.
  Vol.5 No.1 pp.57-68
  Abstract Link to IOS Press
• P.B. Endecott and S.B. Furber
  Modelling and Simulation of Asynchronous Systems using the LARD Hardware Description Language
  Proceedings of the 12th European Simulation Multiconference, Manchester, June 1998, Society for Computer Simulation International, pages 39-43. ISBN 1-56555-148-6.
  Abstract PDF (279K).
• S. Mohammadi, F. Devos, D. Dulac, A. Merigot
  Current-sensing device for completion detection
  International Journal of Electronics Vol.85 No.3 pp.337-344
  Abstract PDF (© 1998 Taylor & Francis Ltd.).
• M. Lewis, J. Garside, L. Brackenbury
  Re-configurable Latch Controllers for Low Power Asynchronous Circuits
  Proceedings of 1st UK Low Power Forum, Sheffield, September 1998, pp. 5.1-5.5
  
• S.B. Furber, J.D. Garside, D.A. Gilbert
  AMULET3: A High-Performance Self-Timed ARM Microprocessor
  Proceedings ICCD'98, Austin, Texas, 5-7 October 1998, pp. 247-252
  ISBN 0-8186-9099-2
  Abstract PDF (32K). IEEE Copyright
• P.B. Endecott and S.B. Furber
  Behavioural Modelling of Asynchronous Systems for Power and Performance Analysis
  Proceedings of PATMOS'98, Lyngby, Denmark, October 6-9.
  Abstract PDF (37K).
• L.E.M. Brackenbury
  Optical solution to the Lee algorithm by use of symbolic substitution
  Applied Optics, Vol. 37, No.17, 1998, pp.3705-3716
  Abstract PDF(323K). © 2002 OPTICSINFOBASE.ORG

1997

• J.V. Woods, P. Day, S.B. Furber, J.D. Garside, N.C. Paver and S. Temple
  AMULET1: An Asynchronous ARM Microprocessor
  IEEE Transactions on Computers Vo. 46 No. 4 pp. 385-398
  April 1997
  ISSN: 0058-9340
  Abstract PDF (696K). IEEE Copyright
• D.A. Gilbert, J.D. Garside
  A Result Forwarding Mechanism for Asynchronous Pipelined Systems
  Proceedings Async '97 pp. 2-11 IEEE Computer Society Press
  April 1997
  ISBN: 0-8186-7922-0
  Abstract PDF (884K). IEEE Copyright
• O. A. Petlin, S. B. Furber
  Built-In Self-Test Design of Micropipelines
  Proceedings Async '97 pp. 22-29 IEEE Computer Society Press
  April 1997
  ISBN: 0-8186-7922-0
  Abstract PDF (724K). IEEE Copyright
• S.B. Furber, J.D. Garside, S. Temple, J. Liu, P. Day, N.C. Paver
  AMULET2e: An Asynchronous Embedded Controller
  Proceedings Async '97 pp. 290-299 IEEE Computer Society Press
  April 1997
  ISBN: 0-8186-7922-0
  Abstract PDF (920K). IEEE Copyright
• A. Bardsley and D.A. Edwards
  Compiling the Language Balsa to Delay Insensitive Hardware.
  Proceedings CHDL'97, Toledo, April 1997
  Published in: Hardware Descriptions Languages and their Applications.
  Ed. C. D. Kloos & E. Cerny, pub. IFIP & Chapman Hall, 1997 pp. 89-91.
  ISBN 01412 78810 1
  Abstract PDF (11K).
• S.B. Furber
  Britain needs Manufacturing.
  IEE Computing & Control Engineering Journal, Vol. 8, No. 2,
  April 1997, pp. 89-90
• G.K. Theodoropoulos, G.K. Tsakogiannis and J.V. Woods
  Occam: An Asynchronous Hardware Description Language?
  Proceedings of the 23rd IEEE Euromicro Conference on New Frontiers of Information Technology, Budapest, Hungary, IEEE Computer Society, ISBN 0-8186-8129-2
  September 1997, pp. 249-256.
  Abstract PDF (377K).
• D.L. Jackson, R. Kelly and L.E.M. Brackenbury
  Differential register bank design for self timed differential bipolar technology
  IEE Proceedings - Circuits Devices & Systems, Vol. 144, No. 5,
  October 1997, pp. 297-302.
  Abstract PDF (797K)
• R. Kelly and L.E.M. Brackenbury
  Design and modelling of a high performance differential bipolar self-timed microprocessor
  IEE Proceedings - Computers and Digital Techniques, Vol. 144, No. 6,
  November 1997, pp. 371-380.
  Abstract PDF (1110K)

1996

• G. Theodoropoulos, J.V. Woods
  Simulating Asynchronous Architectures on Transputer Networks
  IEEE EUROMICRO Workshop on Parallel and Distributed Processing 1996
  Braga, Portugal, January 24-26, 1996.
  Abstract PDF (318K)
• S.B. Furber
  Asynchronous Logic
  IberChip, Sao Paulo, Brazil, 12 Feb 1996.
  Abstract PDF (202K).
• S.B. Furber
  Breaking Step - the Return of Asynchronous Logic
  Keynote talk - IEE Colloquium on the Design and Test of Asynchronous Systems
  Savoy Place, London, 28 February 1996, pp. 1/1 - 1/4
  UK ISSN 0963-3308 ref 1996/040
  PDF(17K)
• Design for Testability of an Asynchronous Adder
  O. A. Petlin, C. Farnsworth, S. B. Furber
  Proc. of IEE Colloquium on Design and Test of Asynchronous Systems,
  London, UK, 28 Feb., 1996, pp. 5/1- 5/9
  Abstract PDF(59K).
• J.D. Garside, S. Temple, R. Mehra
  The AMULET2e Cache System
  Proceedings: Async'96
  Aizu-Wakamatsu, Japan, March 18-21 1996.
  Abstract PDF (135K). IEEE Copyright
• S.B. Furber and J. Liu
  Dynamic Logic in Four-Phase Micropipelines
  Proceedings: Async'96
  Aizu-Wakamatsu, Japan, March 18-21 1996.
  Abstract PDF (44K). IEEE Copyright
• S.B. Furber and P. Day
  Four-Phase Micropipeline Latch Control Circuits
  IEEE Transactions on VLSI Systems, vol. 4 no. 2, June 1996 pp. 247-253.
  ISSN 1063-8210
  Abstract PDF (256K). IEEE Copyright
• Garside J.D.
  AMULET2e
  Symposium Record of Hot Chips 8, Stanford University, CA, U.S.A., August, 1996
• R.M.Davies and J.V.Woods
  Timing Verification for Asynchronous Design
  Proceeedings of the European Design Automation Conference, EURO-DAC'96,
  Geneva, Switzerland, Sept. 1996, pp 78-83. IEEE Computer Society Press,
  (ISBN 0-8186-7573-X)
  Abstract PDF (56K).
• S.B. Furber, P. Day, J.D. Garside, N.C. Paver and S. Temple
  AMULET2e
  EMSYS'96 - OMI Sixth Annual Conference
  Berlin, 23-25 September 1996. IOS Press
  ISBN 90 5199 300 5
  Abstract PDF (728K).
• P.B. Endecott
  Superscalar instruction issue in an asynchronous microprocessor
  IEE Proceedings on Computers and Digital Techniques,
  Volume 143, Number 5, September 1996.
  ISSN 1350-2387.
  Abstract PDF (47K).

1995

• O.A. Petlin, S.B. Furber
  Scan testing of asynchronous sequential circuits
  Proceedings: Fifth Great Lakes Symp. on VLSI
  Buffalo, N.Y., USA, Mar. 16-18, 1995.
  Abstract PDF (38K) IEEE Copyright
• O.A. Petlin, S.B. Furber
  Scan testing of micropipelines
  Proceedings: 13th IEEE VLSI Test Symposium Princeton, New Jersey, USA, May 1-3, 1995.
  Abstract PDF (40k) IEEE Copyright
• P. Day, J.V. Woods
  Investigations into Micropipeline Latch Design Styles
  IEEE Transactions on VLSI Systems
  Vol. 3, No. 2, pp. 264-272, June 1995
  ISSN: 1063-8210.
  Abstract PDF (932K) IEEE Copyright
• O. A. Petlin, S. B. Furber, A. M. Romankevich, V. V. Groll
  Designing Asynchronous Sequential Circuits for Random Pattern Testability
  IEE Proc.-Comput. Digit. Tech., Vol. 142, No. 4, July 1995.
  Abstract PDF(96K).
• G. Theodoropoulos, J.V. Woods
  Dealing with Time Modelling Problems in Parallel Models of Asynchronous Computer Architectures
  Proceedings of the World Transputer Congress 1995, The Transputer Consortium (TTC), Harrogate, West Yorkshire, UK, September 4-6, 1995, pp. 457-472.
  Abstract PDF (211K)
• G. Theodoropoulos, J.V. Woods
  Analysing the Timing Error in Distributed Simulations of Asynchronous Computer Architectures
  Proceedings of the Eurosim Congress '95, TU Vienna, September 11-15, Vienna, Austria, pp. 529-534.
  Abstract PDF (118K)
• D.J. Kinniment, J.D. Garside, B. Gao
  A Comparison of Power Consumption in some CMOS Adder Circuits
  Proceedings: PATMOS'95
  Oldenburg, Germany, October 4-6 1995.
  Abstract PDF (129K).
• R. Mehra, J.D. Garside
  A Cache Line Fill Circuit for a Micropipelined Asynchronous Microprocessor
  IEEE Computer Society, TCCA Newsletter October 1995.
  Abstract PDF (40K).
• P.B. Endecott
  Parallel Structures for Asynchronous Microprocessors
  IEEE Computer Society, TCCA Newsletter, October 1995
  Abstract PDF (30K).
• O. A. Petlin, S. B. Furber
  Designing C-elements for Testability
  Technical Report UMCS-95-10-2, School Of Computer Science, University of Manchester, UK, 1995.
  Abstract PDF (1310K)

1994

• S.B. Furber, P. Day, J.D. Garside, N.C. Paver and J.V. Woods
  AMULET1: A Micropipelined ARM
  Proceedings of CompCon'94, pp.476-485, IEEE Computer Society Press, CompCon'94, San Francisco, March 1994
  Abstract PDF (59K)
• L.E.M. Brackenbury, S.B. Furber, R. Kelly
  Transforming Architectural Models Into High Performance Concurrent Implementations
  1994 UK IT Forum Conference Digest, pp. 9 - 16
  Heriot-Watt University, Edinburgh, UK March 1994
  Abstract PDF (25K)
• G. Theodoropoulos, J.V. Woods
  Building Parallel Distributed Models for Asynchronous Computer Architectures
  Proceedings of the World Transputer Congress 1994, Como, Italy, September 1994, pp 285-301.
  Abstract PDF (99K)
• G. Theodoropoulos, J.V. Woods
  Distributed Simulation of Asynchronous Computer Architectures: The Program Driven Conservative Approach
  Proceedings of the European Simulation Symposium 1994, Volume 2, Istanbul, Turkey, October 1994, pp 230-234.
  Abstract PDF (152K)
• S.B. Furber, P. Day, J.D. Garside, N.C. Paver, S. Temple and J.V. Woods
  The Design and Evaluation of an Asynchronous Microprocessor
  Proceedings of ICCD 94 (1994) pp 217-220.
  ICCD '94 Boston, Massachusetts Oct. 10-12th 1994.
  Abstract PDF (26K)
• Aaron Ashkinazy, Doug Edwards, Craig Farnsworth, Gary Gendel and Shiv Sikand
  Tools for Validating Asynchronous Digital Circuits
  Proceedings of International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Technical Committee on VLSI
  Salt Lake City, Utah, USA Nov. 3-5th 1994.
  Abstract PDF (72K)
• Craig Farnsworth, Doug Edwards, Shiv Sikand
  Utilising Dynamic Logic for Low Power Consumption in Asynchronous Circuits
  Proceedings of International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Technical Committee on VLSI
  Salt Lake City, Utah, USA Nov. 3-5th 1994.
  Abstract PDF (125K)

1993

• Garside J.D.
  A CMOS VLSI Implementation of an Asynchronous ALU,
  Proceedings of the IFIP Working Conference on Asynchronous Design Methodologies, Manchester, England (1993).
  Abstract PDF(142K)
• Furber S.B.
  Breaking Step - the Return of Asynchronous Logic.
  IEE Review, July 1993.
• Furber S.B.
  AMULET1 - An Asynchronous ARM Processor.
  Symposium Record of Hot Chips V, Stanford University, CA, U.S.A., August, 1993.
• Furber S.B.
  Computing without Clocks.
  Proceedings of the VII Banff Workshop: Asynchronous Hardware Design, Banff, Canada, 1993.
• Furber, S.B., Day, P., Garside, J.D., Paver, N.C. and Woods, J.V.
  A Micropipelined ARM
  Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration (VLSI'93), Grenoble, France, September 1993. Ed. Yanagawa, T. and Ivey, P.A. Pub. North Holland.
  Abstract PDF (205K)

1992

• Edwards D.A.
  Pitfalls in Asynchronous Design.
  AMULET Group Internal Report, 1992.
• N.C. Paver, P. Day, S.B. Furber, J.D. Garside and J.V. Woods,
  Register Locking in an Asynchronous Microprocessor
  Proceedings of ICCD 92 (1992) pp 351-355.
  Abstract PDF (232K)